userbinator comments on “VHDL or Verilog?”

Whenever the VHDL vs Verilog argument is brought up, I am reminded of this competition from a long time ago:

http://athena.ecs.csus.edu/~changw/class_docs/VerilogManual/…

(Notice which language won, who won, and what company he worked for…)


link

userbinator

Source:
https://news.ycombinator.com/item?id=14236762